First of all, what happened to the nice forum I was reading before I created an account, that I could navigate, sorry, this web interface has too much going on, I can’t figure out where to post, so sorry…
I’m trying to work through creating a Vitis/Vivado 2020.1 FreeRTOS project using all 4 network adapters. I got the Vivado part down, I think by running the TCL script for Vivado 2019.2. So, I got bitstream and XSA file. I added in the LWIP and other driver changes into a local repository and can generate the BSP. However, when I try to create an application project (TCP Echo server), I can not click “finish” and I get a warning that LWIP should be included, but it is.
I’m sure some stupid change or update needs to happen, but at this point I’m at a loss as to what…
Anybody know the missing step or have created a FreeRTOS/lwip project using the QuadEthernet board for Ultra96?
Thanks, for your help
(p.s. It is really distracting to be typing one place and seeing two places update ---- this is really some crazy stuff going on)
