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CHRP ISA DMA Controller Device Binding
CHRP(TM) ISA DMA Controller
Device Binding to
IEEE 1275-1994
Standard for Boot (Initialization,
Configuration) Firmware
Revision: 1.0 Unapproved DRAFT
May 21,1996
Table of Contents
This document specifies the application of Open Firmware to the PowerPC Common Hardware Reference Platform (CHRP) ISA DMA controller, including device-specific requirements and practices for initialization, properties, and methods. This device shall be a child of an ISA or EISA Bus.
Revision 1.0 Unapproved DRAFT , Initial revision. Jordan Brown, Sunsoft and John Kingman, IBM editors
This Open Firmware System binding standard shall be used in conjunction with the following publications. When the following standards are superseded by an approved revision, the revision shall apply.
- [1]
- IEEE Std 1275-1994 Standard for Boot (Initialization, Configuration) Firmware, Core Practices and Requirements.
- [2]
- Core Errata, IEEE P1275.7/D4.
- [3]
- ISA/EISA/ISA-PnP binding to: IEEE Std 1275-1994, Standard for Boot (Initialization, Configuration) Firmware.
- [4]
- Device Support Extensions to: IEEE Std 1275-1994, Standard for Boot (Initialization, Configuration) Firmware.
- [5]
- PowerPC Microprocessor Common Hardware Reference Platform: I/O Device Reference. This document describes the PowerPC Common Hardware Reference Platform (CHRP) System Standard I/O Devices; hardware registers, register locations, and hardware attributes.
- [6]
- Open Firmware Recommended Practice: Interrupt Mapping.
- [7]
- Open Firmware Recommended Practice: Generic Names.
- [8]
- PowerPC Microprocessor Common Hardware Reference Platform binding to: IEEE Std 1275-1994, Standard for Boot (Initialization, Configuration) Firmware.
EISA: Extended Industry Standard Architecture
ISA: Industry Standard Architecture
The Direct Memory Access (DMA) controller helps ISA devices transfer data directly to and from memory. The DMA controller is logically two controllers designated DMA Controller 1 and DMA Controller 2. DMA Controller 1 provides four DMA channels (designated channels 0-3) which are capable of 8 bit DMA transfers. Controller 2 provides four DMA channels (designated channels 4-7) of which channels 5-7 are capable of 16 bit DMA transfers. Channel 4 is used for cascading DMA Controller 1 to DMA Controller 2 and is unusable for data transfer with an ISA device. Refer to [5] for a complete description of the device's capabilities and interfaces.
None.
As specified in [1], [3] and [8], with the following additions or modifications.
"name" S
Standard property name, specifies the generic name of the device.
The meaning of this property is as defined in Open Firmware core document [1], as modified by the Generic Names Recommended Practice [7]. The value for nodes described by this specification shall be "dma-controller".
"device_type" S
Standard property name to define the device's implemented interface.
The meaning of this property is as defined in the Open Firmware core document [1]. The value for nodes described by this specification shall be "dma-controller".
"compatible" S
Standard property name, specifies device names with which this device is compatible.
The meaning of this property is as defined in Open Firmware, as modified by the Generic Names Recommended Practice [7]. As described in those documents, the entries are a list of device names with which this device is compatible, starting with the name of the device itself and progressing through successively less precise and possibly less functional compatible devices.
The value of this property shall include "chrp,dma"
Additional entries may be supplied, at their appropriate position in the list, to describe devices with which this device is compatible.
"reg" S
Standard property name to define the package's registers.
The meaning of this property is as defined in the Open Firmware core document [1]. It describes the device's register set. The values which shall be assigned to this property are explained in the ISA/EISA/ISA-PnP binding[3] and the I/O Device Reference[5].
"interrupts" S
Standard property name to define the package's interrupts, if any.
The meaning of this property is as defined in the Interrupt Mapping Recommended Practice [6]. The values assigned to this property are explained in the ISA/EISA/ISA-PnP binding[3] and the I/O Device Reference[5]. The value of this property shall correspond to IRQ13 of the ISA interrupt controller.
"dma" S
Standard property name to define reserved DMA channels.
The values assigned to this property are explained in the ISA/EISA/ISA-PnP binding[3] and the I/O Device Reference[5]. The value of this property shall be a list of ISA DMA channels which cannot be assigned due to cascading, wiring, or other reasons. Only the dma# part of the property is pertinent to this use.
None.
As specified in [1] and [3], without addition or modification.
As specified in [1] and [3], without addition or modification.
None.
None.
None.
For devices not selected as Open Firmware's "console input device" or "console output device" device, most of the initial state is typically undefined. For this device, the registers may be undefined, but all interrupts and DMA channels shall be disabled when the client is started.
Refer to [5] for more information on the state of this device when the client is started.
For devices not selected as Open Firmware's "console input device" or "console output device" device, there is no requirement. Typically, this device is unsuitable for use as an Open Firmware console input or console output device.