How to use JTAG connector on hikey960
Hello,
according to the documentation, to access to jtag I need:
Step 1
Power on and reset the Hi3660.
Step 2
Set JTAG_SEL1 and JTAG_SEL0 to 2’b01 to multiplex the CPU JTAG function on the JTAG pin.
Step3
Set JTAG_SEL1 and JTAG_SEL0 to 2’b00 to enter the register selection mode. Configure the
system control register JTAGSYS_SW_SEL [7:0] to switch to the selected debugging
interface for debugging.
Step 4
Connect the corresponding simulator and open the corresponding debugging software to start
debugging
I have soldered the JTAG connector. I verified my cable and soldering are ok. I have used two different jtag probes but they cannot find the target.
I have localized JTAG_SEL0 and JTAG_SEL1 (TP902 and 903 on the board following the schematics), but how can I configure the system control register JTAGSYS_SW_SEL please? No information about that into the doc.
Please any detail shoulb be nice here.
Regards
I am interested in this as well. While it is possible to pull the two testpoints to the indicated values, there is apparently no information on the control registers JTAGSYS_SW_SEL.
Did anyone achieve this?
The linaro team, or the boot developers should have this information as they developed/adopted the bootloader…
Any detail would be nice 
maybe i’m blind, i see no TP902/3 caption. schematics states near J2301 (jtag conn. itself), but i see there only one testpoint not sure which is it
I am reading same information from manual, did you figure this one out?
Hi all,
Hisilicon has released some Jtag configurations, hope this is helpful for Jtag enabling:
More docs for DS5 enabling on Hikey960 from Hisilicon landing team (also thanks ARM colleagues!):
finaly located test points TP902 TP903
Hi,
So actually where are those test points located ?
I don’t see them around the JTAG connector (there’s maybe one but it’s quite far…)
If you have a picture that would help.
Also I’m not sure to understand the description from the Hisilicon manual.
Should TP902/TP903 be forced to b01 permanently to enable JTAG (that is TP902 to ground, TP903 to VCC??) ?
Is there a SW configuration to be made , JTAGSYS_SW_SEL register to be configured? Is this through debugger, dump window or DAP ??
And can’t see any such SW configuration done from the mentioned scripts …
Thanks for your help.
Do you need the Dstream device to use this. Or can you use any jtag reader and connect it to DS5 ?
Hi,
Following this subject (a few months later), did anyone got JTAG to work on the Hikey960?
If not, did anyone got to a conclusion on what to do with those JTAG_SEL pins or what should we do on the board side to enable JTAG debug?
Kind regards
I read a bit for the two docs:
https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/support/ds-5-jtag-debugging-hikey960.md
https://github.com/96boards-hikey/tools-images-hikey960/blob/master/trace32-jtag-scripts/Hikey960_t32_script.tar.gz
I don’t find any information about configuring JTAGSYS_SW_SEL; want to remind one thing for using JTAG, firstly you must need to disable idle states for all CPUs, please refer the shell script for this: https://github.com/96boards-hikey/tools-images-hikey960/blob/master/ds5-jtag-scripts/close_idle.sh
FWIW, upload the picture for TP902/TP903.
hi,now I am work the openocd with the hikey960
ok, let’s mark it:
I use two type of the jtag tools: jlink v11 edu and the bus blaster v3; the jlink is different ,you must add the srst to connect hi3660;hikey960 board is default not connect ,by the schematic ,you can remove the diode for extern reset to instead it. (D2201–>D2203); or you can short the D2203 is also ok.
by the jlink,if you don’t do this .you run the openocd through the jlink.you will get the all ones error.
but the bus blaster is don’t have this question. it don’t need to modify the board.
tips: don’t care about the tp902 an tp903 jtag sel mux;it default works ok.
next you need to edit the target cfg file like bellow:
SPDX-License-Identifier: GPL-2.0-or-later
Hisilicon Hi3660 Target
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME hi3660
}
Main DAP
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}
declare the one JTAG tap to access the DAP
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
create the DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
declare the 8 main application cores
set _TARGETNAME $_CHIPNAME.cpu
set _smp_command “”
set $_TARGETNAME.cti(0) 0x80C20000
set $_TARGETNAME.cti(1) 0x80D20000
set $_TARGETNAME.cti(2) 0x80E20000
set $_TARGETNAME.cti(3) 0x80F20000
set $_TARGETNAME.cti(4) 0x81420000
set $_TARGETNAME.cti(5) 0x81520000
set $_TARGETNAME.cti(6) 0x81620000
set $_TARGETNAME.cti(7) 0x81720000
set $_TARGETNAME.dbg(0) 0x80C10000
set $_TARGETNAME.dbg(1) 0x80D10000
set $_TARGETNAME.dbg(2) 0x80E10000
set $_TARGETNAME.dbg(3) 0x80F10000
set $_TARGETNAME.dbg(4) 0x81410000
set $_TARGETNAME.dbg(5) 0x81510000
set $_TARGETNAME.dbg(6) 0x81610000
set $_TARGETNAME.dbg(7) 0x81710000
set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
set _command "target create ${_TARGETNAME}$_core aarch64 \
-dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
-dbgbase [set $_TARGETNAME.dbg($_core)]"
if { $_core != 0 } {
# non-boot core examination may fail
set _command "$_command -defer-examine"
set _smp_command "$_smp_command ${_TARGETNAME}$_core"
} else {
# uncomment when "hawt" rtos is merged
# set _command "$_command -rtos hawt"
set _smp_command "target smp ${_TARGETNAME}$_core"
}
eval $_command
}
eval $_smp_command
Make cpu0 the default target
targets ${_TARGETNAME}0
Examine secondary cores
proc xs {} {
global _TARGETNAME
for { set _core 1 } { $_core < 8 } { incr _core 1 } {
${_TARGETNAME}$_core arp_examine
}
}
before you use openocd ,you need plug usb to your compute. and use adb commond:
adb root
adb shell ./system/close_idle.sh
the file close_idle.sh you can find the linaro website.
and last the openocd need add the arm v8 patch ,just follow :
clone the openocd code.
get the patch:
wget ‘https://review.openocd.org/gitweb?p=openocd.git;a=patch;h=dd5e2fb9290628e21a90b6681e9318cdc79df5ca’ -O patch_arm_v8
git am patch_arm_v8;
then compile ,you will get the openocd;
just run ,like this:
/openocd -f …/share/openocd/scripts/interface/ftdi/dp_busblaster_kt-link.cfg -f …/cfg/hi3660.cfg or
/openocd -f …/share/openocd/scripts/interface/jlink.cfg -f …/cfg/hi3660.cfg
you will success get this:
pen On-Chip Debugger 0.12.0-00001-g5b042ece8 (2024-04-20-08:45)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
jtag
xs
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Warn : An adapter speed is not selected in the init scripts. OpenOCD will try to run the adapter at the low speed (100 kHz)
Warn : To remove this warnings and achieve reasonable communication speed with the target, set “adapter speed” or “jtag_rclk” in the init scripts.
Info : clock speed 100 kHz
Info : JTAG tap: hi3660.tap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x5)
Info : hi3660.cpu0: hardware has 6 breakpoints, 4 watchpoints
Info : starting gdb server for hi3660.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Info : accepting ‘telnet’ connection on tcp/4444
Info : hi3660.cpu1: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu2: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu3: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu4: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu5: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu6: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu7: hardware has 6 breakpoints, 4 watchpoints
Info : hi3660.cpu0 cluster 0 core 0 multi core
Info : hi3660.cpu1 cluster 0 core 1 multi core
ok good luck.
